Encoding
Each mips instruction is a fixed length of 32 bits. Each register that is in letters will be translated into numbers from 0-31 (32 register). We need 5 bits for the register.
Opcode - Specifies the instruction
funct - Combine with opcode to specify the inst more
rs - source register
rt - target
rd - destination
shamt - amount a shift instruction will shift by
R format
(Register format: op $r1, $r2, $r3)
Use 2 source register, 1 destination register (3 Reg)
e.g add, sub, and, or ,nor, slt
Special : srl,sll
Fields:
6/5/5/5/5/6
opcode/rs/rt/rd/shamt/funct
add $8, $9,$10
add rd,rs,rt
for sll, the shamt would contain the number of bits needed to shift (not 2 complements)
e.g 2=> 00010
e.g 2=> 00010
I Format
(Immediate format: op $r1,$r2, immd)
Use 1 source, 1 immediate and 1 destination register
Its partially consistent with R format.
Its partially consistent with R format.
e.g addi
For LW/SW,
LW $t0, 0($s1)
For LW/SW with 0($s1), the 0 is the immediate and $s1 is source register, $t0 is rt
For LW/SW,
LW $t0, 0($s1)
For LW/SW with 0($s1), the 0 is the immediate and $s1 is source register, $t0 is rt
Fields:
6/5/5/16
opcode/rs/rt/immediate
addi $21, $22, -50
op rs, rt , immd (2s)
8 22 21 -50
For load word, the offset is stored in the immediate.
We can observed that everytime we multiply by 4 we will end up with 2 zeros and since the instructions are word aligned hence are in multiples of 4, we do not need to store the last two zeros
Now we can handle loops 4 times larger.
The computer would automatically add the 2 0s when it reads the immediate. Thus immediate can be stored as a 2^17 due to the extra 0s
Finding Hexadecimal representation of I format
1. Convert opcode
2. Convert source/target register based on register number (not values stored)
e.g &t8 -> 24(decimal) in binary
3. Convert immediate to 2 complements
4. Put them together
J Format
(Jump format: op immd)
J instruction uses only one immediate value
J can jump to anywhere in memory therefore we must have the entire 32 bit.
Similar to I format, we can assume the last two bits to be gone and due to consistency with all the address ending with 2 0s.
J can jump to anywhere in memory therefore we must have the entire 32 bit.
Similar to I format, we can assume the last two bits to be gone and due to consistency with all the address ending with 2 0s.
Fields
6/26
opcode/target address
Optimization:
There is only 26 bits left so we can optimise to 28 by ignoring the last 2 bits due to consistency of all address ending with 2 0s.
For the missing front 4 bits, it is taken from the PC, the address first byte. (Most sig 4 bits of PC)
2^28 is 256 MB, thus we can only jump within 256 MB range (128MB up/down)
Special instruction is needed if we want to jump outside this boundary. (JR instr)
Finding target address
1. Check the first 4 bit, if they share then we can encode.
2. Add 2 0s
3. Take the rest of the 26 bits and put it into the immediate (target address)
Finding hexadecimal representation of Jump Instruction
Assuming we have address of jump instruction
1. Count number of instruction from jump instruction physically
2. Convert address of Jump instruction to binary
3. Remove 2 0s at the back
4. Add/Subtract the number of jumps from Jump instruction address
->this is to get target address
5. Remove first 4 bits
6. Add opcode of jump
7. Convert back to Hex
Instruction has memory address also
A register that keeps address of instruction being executed in processor
After every instruction, it adds 4 bytes. Instructions are 32 bits long (word align).
Branching
beq $9,$0 ,loop
The loop label is an address.
But the immediate is only 16 bits but our memory address is 32 bits.
(Not enough)
A branch changes the PC by a small amount. So we will specify target address relative to the PC.
Target address = PC + 16 bit imme field (can be -ve or +ve depending on direction)
Forward is positive, backwards is negative
Calculating the number of instruction:
[+-]2^15 bytes (Immediate size)/ 4 bytes (size of one instruction) = number of instruction between jumps
Enlarging it
We can observed that everytime we multiply by 4 we will end up with 2 zeros and since the instructions are word aligned hence are in multiples of 4, we do not need to store the last two zeros
Now we can handle loops 4 times larger
Only branches interpret the immediate as bytes.
Address calculation (LW/SW/BNE/BEQ/J)
Only for Branching:
If branch is not taken (condition not pass):
PC = PC +4
PC + 4 = address of next instruction
else if branch is taken
pc = (pc +4) + (imm *4)
Counting relative:
Immediate field (Downwards):
1. Move one instruction forward
2. Start counting from the next
Loop: beq $9, $0, END
add ... <- (1)
addi ..... +1 (2)
j loop +2
END: +3
OPCODE: 4
RS: 9
RT:0
Imme: 3
Immediate field (Upwards):
1. Count from myself
2. Start counting from the next
Loop: beq $9, $0, END -4
add ... -3
addi ..... -2
beq $0,$0 loop -1 (2)
END: <- (1)
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Optimization:
There is only 26 bits left so we can optimise to 28 by ignoring the last 2 bits due to consistency of all address ending with 2 0s.
For the missing front 4 bits, it is taken from the PC, the address first byte. (Most sig 4 bits of PC)
2^28 is 256 MB, thus we can only jump within 256 MB range (128MB up/down)
Special instruction is needed if we want to jump outside this boundary. (JR instr)
Finding target address
1. Check the first 4 bit, if they share then we can encode.
2. Add 2 0s
3. Take the rest of the 26 bits and put it into the immediate (target address)
Finding hexadecimal representation of Jump Instruction
Assuming we have address of jump instruction
1. Count number of instruction from jump instruction physically
2. Convert address of Jump instruction to binary
3. Remove 2 0s at the back
4. Add/Subtract the number of jumps from Jump instruction address
->this is to get target address
5. Remove first 4 bits
6. Add opcode of jump
7. Convert back to Hex
Instruction address
Instruction has memory address also
Each memory instruction is 4 byte, that's why the difference between memory address is always 4 bytes.
Program counterA register that keeps address of instruction being executed in processor
After every instruction, it adds 4 bytes. Instructions are 32 bits long (word align).
Branching
beq $9,$0 ,loop
The loop label is an address.
But the immediate is only 16 bits but our memory address is 32 bits.
(Not enough)
A branch changes the PC by a small amount. So we will specify target address relative to the PC.
Target address = PC + 16 bit imme field (can be -ve or +ve depending on direction)
Forward is positive, backwards is negative
Calculating the number of instruction:
[+-]2^15 bytes (Immediate size)/ 4 bytes (size of one instruction) = number of instruction between jumps
Enlarging it
We can observed that everytime we multiply by 4 we will end up with 2 zeros and since the instructions are word aligned hence are in multiples of 4, we do not need to store the last two zeros
Now we can handle loops 4 times larger
Only branches interpret the immediate as bytes.
Address calculation (LW/SW/BNE/BEQ/J)
Only for Branching:
If branch is not taken (condition not pass):
PC = PC +4
PC + 4 = address of next instruction
else if branch is taken
pc = (pc +4) + (imm *4)
Counting relative:
Immediate field (Downwards):
1. Move one instruction forward
2. Start counting from the next
Loop: beq $9, $0, END
add ... <- (1)
addi ..... +1 (2)
j loop +2
END: +3
OPCODE: 4
RS: 9
RT:0
Imme: 3
Immediate field (Upwards):
1. Count from myself
2. Start counting from the next
Loop: beq $9, $0, END -4
add ... -3
addi ..... -2
beq $0,$0 loop -1 (2)
END: <- (1)
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